14 Fully-Funded PhD Scholarship Opportunities with Project REACT (Marie Skłodowska-Curie Doctoral Network)

Are you a Master’s degree holder looking to pursue a PhD in cutting-edge neuromorphic computing and related fields? Project REACT, part of the Marie Skłodowska-Curie Doctoral Network (MSCA DN), offers 14 fully-funded PhD positions across top institutions in Europe and Israel. These positions focus on innovative research in secure, energy-efficient, and sustainable computing technologies. Below, we outline the eligibility criteria, employment conditions, application process, and details of each PhD position to help you find the perfect opportunity.

Eligibility Criteria for Project REACT

To apply for these PhD positions, you must meet the following requirements:

• Doctoral Status: You must be a doctoral candidate without a PhD degree at the time of recruitment. If you’ve defended your thesis but not received the degree, you’re ineligible.
• Mobility Rule: You must not have lived or worked/studied in the host institution’s country for more than 12 months in the 36 months before recruitment (excluding short holidays, national service, or refugee status).
• Educational Background: Hold a Master’s degree (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Prior experience in Project REACT’s research areas is a plus.
• English Proficiency: Strong spoken and written English skills are required, as it’s the official working language.

Employment Conditions

Successful candidates will enjoy:

• Contract: A 36-month full-time employment contract at a Project REACT host institution.
• Salary: A gross monthly salary including a €3,400 Living Allowance (adjusted by MSCA Country Correction Coefficients) and a €600–€1,260 Mobility/Family Allowance based on family status.
• PhD Completion: Expected to complete your PhD by the end of the contract or shortly after.
• Training & Development:
  • Conduct original research aligned with Project REACT themes.
  • Participate in academic courses, workshops, and events for scientific and transferable skills.
  • Undertake research secondments with partner institutions for interdisciplinary experience.
  • Receive supervision from experienced researchers within the MSCA DN.

How to Apply

Follow these steps to apply:

1. Select Projects: Choose up to three preferred PhD projects from the list below, ranking them as 1st, 2nd, and 3rd choices.
2. Prepare Documents: Submit a single PDF including:
   • Detailed CV
   • Cover Letter (explain your suitability, background, and research experience)
   • Research Statement (max 2 pages, detailing your interests and past projects)
   • Copy of your highest degree diploma (optional: academic transcript)
   • Contact details of two referees
3. Submit Application: Use the online Application Form and, if required, the host institution’s recruitment system.
4. Selection Process: Applications are reviewed on a rolling basis. Shortlisted candidates will be invited for online interviews. Only the first application is considered if duplicates are submitted.
5. Key Dates:
   • Application Period: July 1, 2025 – October 30, 2025
   • Recruitment Start: Preferably by November 1, 2025

Note: Host institutions promote diversity and equal opportunity. Additional documents may be required for PhD program enrollment per university regulations.

PhD Scholarship Opportunities

DC1: Secure Neuromorphic Architectures

Institution: University of Groningen, The Netherlands
Description: Develop secure neuromorphic architectures using emerging memory technologies like Resistive RAM (RRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FeRAM), and Phase-Change Memory (PCM). The project focuses on creating security primitives (PUFs, TRNGs), evaluating their performance, and implementing the best candidate via simulation, emulation, and hardware prototyping. Security will be analyzed at device, circuit, and system levels.
Supervisor: Farhad Merchant
Contact: f.a.merchant@rug.nl

DC2: Novel FeRAM/FeFET-Based Neuromorphic Architectures

Institution: University of Groningen, The Netherlands
Description: Explore Ferroelectric RAM (FeRAM) and Ferroelectric Field-Effect Transistors (FeFET) for neuromorphic computing. The project aims to develop and benchmark FeRAM/FeFET-based architectures against state-of-the-art systems to assess their efficiency and commercial viability.
Supervisors: Farhad Merchant, Beatriz Noheda
Contact: f.a.merchant@rug.nl

DC3: Novel Magneto-Resistive Random Access Memory-Based Neuromorphic Architectures

Institution: University of Groningen, The Netherlands
Description: Investigate magnetoresistive devices for energy-efficient neuromorphic computing. Develop system-level simulations and FPGA-based emulation to evaluate performance and benchmark against existing architectures, aiming for future-generation self-aware systems.
Supervisors: Farhad Merchant, Tamalika Banerjee
Contact: f.a.merchant@rug.nl

DC4: Energy-Efficient Online Learning Using Gain-Cell Memory-Based Compute-in-Memory Architecture

Institution: TU Eindhoven, The Netherlands
Description: Create a gain-cell memory-based compute-in-memory (CIM) architecture for energy-efficient online learning at the edge. The project addresses power, latency, and bandwidth constraints by integrating mixed-signal computation and fault detection mechanisms to ensure reliable operation.
Supervisor: Manil Dev Gomony
Contact: m.gomony@tue.nl

DC5: Design Tools, Models, and Circuits for Neuromorphic Computing

Institution: Technion – Israel Institute of Technology, Israel
Description: Develop design tools and circuits for memristive neuromorphic systems using Resistive RAM (ReRAM). The project aims to create a synthesis framework integrating analog and digital layers to enable energy-efficient, brain-inspired computing for edge AI.
Supervisor: Shahar Kvatinsky
Contact: shahar@ee.technion.ac.il

DC6: Adaptive Mixed-Signal Neuromorphic Hardware Accelerator

Institution: Technion – Israel Institute of Technology, Israel
Description: Design a reconfigurable neuromorphic hardware accelerator with adaptable resolution (binary to multi-bit). The project covers the full design cycle, using analog/mixed-signal techniques for energy-efficient, scalable neural computation.
Supervisor: Nicolás Wainstein
Contact: nicolasw@ef.technion.ac.il

DC7: Programming Models and High-Level Compilation for Near-Sensor Dataflow Execution

Institution: TU Dresden, Germany
Description: Develop programming models and compilation methods for reactive applications in cyber-physical systems (CPS). The project builds on MLIR to create a code generation framework optimizing performance, energy efficiency, reliability, and security for neuromorphic accelerators.
Supervisor: Jeronimo Castrillon
Contact: jeronimo.castrillon@tu-dresden.de

DC8: True and Reliable Analog Resistive Switching in 1T1R CMOS-Compatible RRAM Devices

Institution: Leibniz Institute for High Performance Microelectronics (IHP), Germany
Description: Enhance CMOS-compatible RRAM devices for reliable multi-level resistive switching in neuromorphic accelerators. The project involves fabrication, device design, programming algorithms, electrical characterization, and integration into IHP’s Process Design Kit.
Supervisors: Christian Wenger, Tommaso Rizzi
Contact: wenger@ihp-microelectronics.com, rizzi@ihp-microelectronics.com

DC9: Formal Verification for Approximate In-Memory Computing

Institution: University of Bremen, Germany
Description: Develop formal verification methods for approximate in-memory computing (IMC) systems to ensure error bounds and functional correctness. The project focuses on verifying IMC circuits and controllers to enhance reliability.
Supervisors: Rolf Drechsler, Chandan Kumar Jha
Contact: drechsle@uni-bremen.de

DC10: Non-Ideality Tolerant Implementation of a Model of Cortex in a Memristor Fabric

Institution: KTH Royal Institute of Technology, Sweden
Description: Create a scalable Bayesian Confidence Propagation Neural Network (BCPNN) architecture using memristors. The project focuses on synaptic computation, diverse topologies, and resilience against memristor non-idealities for brain-like functions like associative memory.
Supervisor: Ahmed Hemani
Contact: hemani@kth.se

DC12: Sustainable Intelligence at the Edge

Institution: Newcastle University, UK
Description: Combine intermittent computing and neuromorphic architectures for energy-efficient, resilient edge intelligence in IoT and biomedical devices. The project develops a framework for always-on, context-aware processing in energy-constrained environments.
Supervisor: Domenico Balsamo
Contact: domenico.balsamo@ncl.ac.uk

DC13: Post-Quantum Cryptography for Emerging Computing Platforms

Institution: TU Graz, Austria
Description: Investigate post-quantum cryptography (PQC) for secure communication in in-memory computing systems. The project focuses on PQC primitives resistant to quantum attacks, ideal for candidates with cryptography experience.
Supervisor: Sujoy Sinha Roy
Contact: sujoy.sinharoy@iaik.tugraz.at

DC14: FPGA-Accelerated Emulation Framework for Self-Aware Neuromorphic System-on-Chip Architectures

Institution: University of Mons, Belgium
Description: Design an FPGA-based emulation framework for RRAM-based neuromorphic systems. The project maps non-volatile memory, adaptive routing, and on-chip learning, providing energy, latency, and fault-tolerance metrics for edge-intelligent systems.
Supervisor: Carlos Alberto Valderrama
Contact: carlos.valderrama@umons.ac.be

DC15: CMOS-Integrated QRNG for IoT SoC Designs

Institution: iQrypto, Belgium
Description: Develop a CMOS-compatible quantum random number generator (QRNG) for lightweight IoT trusted execution environments. The project includes photon shot-noise circuits, entropy post-processing, and RISC-V SoC integration for secure, low-power edge devices.
Supervisor: Alessandro Brunetti
Contact: a.brunetti@iqrypto.com

Apply Now

Don’t miss this opportunity to join a prestigious MSCA Doctoral Network and advance your research career. Submit your application via the Project REACT Application Form by October 30, 2025. For more details, contact the respective supervisors or visit the host institution’s website.